Method to reduce power consumption of a register file with...

Details Method to reduce power consumption of a register file with... Method to reduce power consumption of a register file with...

2008-05-15

2011-10-25

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C713S323000

Reexamination Certificate

active

08046566

ABSTRACT:
A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.

REFERENCES:
patent: 5179685 (1993-01-01), Nojiri
patent: 7152170 (2006-12-01), Park
patent: 7600101 (2009-10-01), Soltis, Jr.
patent: 2006/0001468 (2006-01-01), Siegler et al.
“Impact of Dynamic Allocation of Physical Register Banks For An SMT Processor” Kato et al. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. 1527-1366/04 IEEE, The Computer Society.

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