Method of achieving timing closure in digital integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C370S238000

Reexamination Certificate

active

07743355

ABSTRACT:
Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

REFERENCES:
patent: 4495559 (1985-01-01), Gelatt et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 6327552 (2001-12-01), Nemani et al.
patent: 6408428 (2002-06-01), Schlansker et al.
patent: 6480991 (2002-11-01), Cho et al.
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6618849 (2003-09-01), Teig et al.
patent: 6717921 (2004-04-01), Aggarwal et al.
patent: 6721924 (2004-04-01), Patra et al.
patent: 6765981 (2004-07-01), Heumann
patent: 6766504 (2004-07-01), Rahut et al.
patent: 6826733 (2004-11-01), Hathaway et al.
patent: 7003747 (2006-02-01), Zhou et al.
patent: 7111268 (2006-09-01), Anderson et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2004/0158807 (2004-08-01), Hossain et al.
patent: 2004/0243964 (2004-12-01), McElvin et al.
Conn et al.; “Gradient-based optimization of custom circuits using a static-timing formulation”; Design Automation Conference, 1999. Proceedings 36th; Jun. 21-25, 1999; pp. 452-459.
Conn et al.; “Overview of Continuous Optimization Advances and Applications to Circuit Tuning”, Proceedings of the 2001 international symposium on Physical design, Apr. 1-4, 2001, Sonoma, California, US, pp. 74-81.
Bai et al., “Uncertainty-Aware Circuit Optimization”, DAC2002, Jun. 10-14, 2002, New Orleans, Louisiana, USA, pp. 58-63.
“Custom Circuit Design as a Driver of Microprocessor Performance”, D.H. Allen et al. http://www.research.ibm.com/hournal/rd/446/allen/html.
“Thermistor Macro”, Thermistor Macro-Fall 1998, http://www.spectrum-soft.com
ews/fall98/therm.shtm.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of achieving timing closure in digital integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of achieving timing closure in digital integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of achieving timing closure in digital integrated... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4248975

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.