Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-19
2010-06-22
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C370S238000
Reexamination Certificate
active
07743355
ABSTRACT:
Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
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Hathaway David J.
Visweswariah Chandramouli
Williams Patrick M.
Zhou Jun
Cantor & Colburn LLP
International Business Machines - Corporation
Kinnaman, Jr. William A.
Levin Naum B
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