Method and apparatus for hardware enforced virtual...

Details Method and apparatus for hardware enforced virtual... Method and apparatus for hardware enforced virtual...

2009-03-09

2010-06-15

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S158000, C711S221000, C709S216000, C709S229000, C370S394000

Reexamination Certificate

active

07739452

ABSTRACT:
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded. Memory read data is returned speculatively since the packet processing engine is processing packets in parallel and not necessarily in sequence. Information is maintained allowing the detection of a speculative read that was incorrect (i.e. a memory conflict). When a memory conflict is detected, a restart signal is generated and the information for the associated packet identifier or sequence number is flushed.

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