Time-multiplexed routing for reducing pipelining registers

Details Time-multiplexed routing for reducing pipelining registers Time-multiplexed routing for reducing pipelining registers

2007-05-16

2010-11-02

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S320000, C713S400000, C713S401000, C713S500000, C713S501000, C713S502000, C713S503000, C367S098000, C379S388030, C379S390030

Reexamination Certificate

active

07827433

ABSTRACT:
Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.

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