Technique for interconnecting integrated circuits

Details Technique for interconnecting integrated circuits Technique for interconnecting integrated circuits

2008-11-10

2010-11-02

Phan, Raymond N (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S306000

Reexamination Certificate

active

07827336

ABSTRACT:
Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.

REFERENCES:
patent: 5805865 (1998-09-01), Mimura et al.
patent: 6397354 (2002-05-01), Ertekin
patent: 6717276 (2004-04-01), Walter et al.
patent: 6845027 (2005-01-01), Mayer et al.
patent: 6877114 (2005-04-01), Allen et al.
patent: 7279795 (2007-10-01), Periaman et al.
patent: 7288434 (2007-10-01), Karnezos
patent: 2003/0052712 (2003-03-01), Comer
patent: 2003/0209740 (2003-11-01), Miyamoto et al.
patent: 2005/0017341 (2005-01-01), Egerer
patent: 2006/0061953 (2006-03-01), Le
U.S. Appl. No. 12/026,325, filed with the USPTO Feb. 5, 2008, listing Perry H. Pelley, III as the first named inventor.
PCT Search Report and Written Opinion, PCT/US2009/062469, Mailed Date Jun. 1, 2010.

Affiliated with

Also associated with

Rating

Technique for interconnecting integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technique for interconnecting integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for interconnecting integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4245546