Semiconductor device, method of manufacturing same and...

Details Semiconductor device, method of manufacturing same and... Semiconductor device, method of manufacturing same and...

Filed on

2007-10-03

Date issued

2010-06-22

Examiner

Tran, Tan N (Department: 2826)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257S347000, C257S348000, C257S369000, C257SE27112

Type

Reexamination Certificate

Status

active

Patent number

07741679

Description

ABSTRACT:
A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

REFERENCES:
patent: 5125007 (1992-06-01), Yamaguchi et al.
patent: 5355012 (1994-10-01), Yamaguchi et al.
patent: 5463238 (1995-10-01), Takahasu et al.
patent: 5621239 (1997-04-01), Horie et al.
patent: 5652454 (1997-07-01), Iwamatsu et al.
patent: 5767549 (1998-06-01), Chen et al.
patent: 5801080 (1998-09-01), Inoue et al.
patent: 5808346 (1998-09-01), Ueda
patent: 5877049 (1999-03-01), Liu et al.
patent: 5889293 (1999-03-01), Rutten et al.
patent: 5985733 (1999-11-01), Koh et al.
patent: 6100570 (2000-08-01), Saito
patent: 6198134 (2001-03-01), Inoue et al.
patent: 6252281 (2001-06-01), Yamamoto et al.
patent: 6351014 (2002-02-01), Inoue et al.
patent: 6403405 (2002-06-01), Kawanaka et al.
patent: 6452232 (2002-09-01), Adan
patent: 6727552 (2004-04-01), Inoue et al.
patent: 6841828 (2005-01-01), Kawanaka et al.
patent: 2002/0098643 (2002-07-01), Kawanaka et al.
patent: 2002/0127784 (2002-09-01), Kawanaka et al.
patent: 2004/0135211 (2004-07-01), Inoue et al.
patent: 0 709 893 (1996-05-01), None
patent: 0 725 407 (1996-08-01), None
patent: 0962988 (1999-08-01), None
patent: 1 339 095 (1973-11-01), None
patent: 57-102067 (1982-06-01), None
patent: 58-124243 (1983-07-01), None
patent: 6-291265 (1994-10-01), None
patent: 7-74363 (1995-03-01), None
patent: 8-172199 (1996-07-01), None
patent: 8-330541 (1996-12-01), None
patent: 9-260679 (1997-10-01), None
patent: 10-189978 (1998-07-01), None
patent: 10-242470 (1998-09-01), None
patent: 11-330473 (1999-11-01), None
patent: 11-340465 (1999-12-01), None
patent: 2000-174283 (2000-06-01), None
patent: 1995-0007575 (1995-07-01), None
patent: 1998-005383 (1998-03-01), None
patent: 1998-081093 (1998-11-01), None
patent: 1998-083989 (1998-12-01), None
patent: 10-0233286 (1999-12-01), None
W. Chen, et al., Symposium on VLSI Technology Digest of Technical Papers, pp. 92-93, “Suppression of the SOI Floating-Body Effects by Linked-Body Device Structure,” 1996.
T. Hashmoto, et al., pp. 209-212, IEDM, “A 0.2-μm Bipolar-CMOS Technology on Bonded SOI With Copper Metallization for Ultra High-Speed Processors,” 1998.
K. Mistry, et al., p. 583, IEDM, “A 2.0V, 0.35 μm Partially Depleted SOI-CMOS Technology,” 1997.
J.A. Mandelman, et al., pp. 164-165, Proceedings 1997 IEEE International SOI Conference, “SOI MOSFET Mismatch Due to Floating-Body Effects,” Oct. 1997.
H. Lee, et al., pp. 63-64, Proceedings 1998 IEEE International SOI Conference, “A New SOI Structure for Mixed Mode IC'S and Its Body-Related Characteristics,” Oct. 1998.
R.L. Woodruff et al., “A Differential-Height-Mesa Buried Tie SOI Process” (1991) pp. 148-149.

Affiliated with

Also associated with

Rating

Semiconductor device, method of manufacturing same and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, method of manufacturing same and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device, method of manufacturing same and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4244853