Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2009-05-18
2010-06-15
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S039000, C326S040000
Reexamination Certificate
active
07737723
ABSTRACT:
In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.
REFERENCES:
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 6028449 (2000-02-01), Schmitt
patent: 6218858 (2001-04-01), Menon et al.
patent: 6507211 (2003-01-01), Schultz
patent: 6573748 (2003-06-01), Trimberger
patent: 6624656 (2003-09-01), Fox et al.
patent: 6717433 (2004-04-01), Barbier et al.
patent: 6851047 (2005-02-01), Fox et al.
patent: 6870397 (2005-03-01), Fox et al.
patent: 6924663 (2005-08-01), Masui et al.
patent: 7088132 (2006-08-01), Tang et al.
patent: 7095247 (2006-08-01), Tang et al.
patent: 7099227 (2006-08-01), Zhou
patent: 7102555 (2006-09-01), Collins et al.
patent: 7111217 (2006-09-01), Schultz
patent: 7180776 (2007-02-01), Wennekamp et al.
patent: 7199608 (2007-04-01), Trimberger
patent: 7218137 (2007-05-01), Vadi et al.
patent: 7366306 (2008-04-01), Trimberger
patent: 7373668 (2008-05-01), Trimberger
patent: 7375549 (2008-05-01), Tang et al.
patent: 7406642 (2008-07-01), Lau
patent: 7480843 (2009-01-01), Jacobson
patent: 7538574 (2009-05-01), Tang et al.
patent: 7554358 (2009-06-01), Tang et al.
patent: 7652500 (2010-01-01), Tang et al.
patent: 2002/0163840 (2002-11-01), Hiraki et al.
patent: 2004/0025086 (2004-02-01), Gorday et al.
patent: 2005/0083743 (2005-04-01), Andrei et al.
patent: 2005/0248364 (2005-11-01), Vadi et al.
patent: 2006/0067102 (2006-03-01), Yamada et al.
Lattice Semiconductor Corporation, “LatticeXP Family Data Sheet,” Version 01.2, Feb. 2005, available at www.latticesemi.com.
Altera Corporation, “Max II Device Handbook,” Version 1.1, Dec. 2004, available at www.altera.com.
Actel Corporation, “ProASIC3E Flash Family FPGAs,” Oct. 2005, available at www.actel.com.
Lattice Semiconductor Corporation, LatticeXP Family Data Sheet, Version 01.2, Feb. 2005, 77 pages.
Altera R, Max II Device Handbook, www.altera.com, M115V1-1.7, 330 pages, no date.
Actel Corporation, ProASICE Flash Family FPGAs, ARM7 TM Soft IP Support in ProASIC3E ARM7-Ready Device, Oct. 2005, 166 pages.
U.S. Appl. No. 10/809,658 Howard Tang.
U.S. Appl. No. 11/243,255 Howard Tang.
U.S. Appl. No. 11/293,941 Howard Tang.
U.S. Appl. No. 11/350,436 Howard Tang.
U.S. Appl. No. 11/397,985, filed Apr. 5, 2006, Fontana et al.
Byrne Jeffrey S.
Tang Howard
Wilkinson Clark
Wong Jack T.
Lattice Semiconductor Corporation
Tan Vibol
LandOfFree
Transparent field reconfiguration for programmable logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transparent field reconfiguration for programmable logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transparent field reconfiguration for programmable logic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4243207