Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-06-07
2010-10-26
Lee, Hsien-ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S455000, C438S459000, C257SE21237
Reexamination Certificate
active
07820495
ABSTRACT:
An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate.
REFERENCES:
patent: 4660062 (1987-04-01), Nishizawa et al.
patent: 4838654 (1989-06-01), Hamaguchi et al.
patent: 5155068 (1992-10-01), Tada
patent: 5306651 (1994-04-01), Masumo et al.
patent: 5382537 (1995-01-01), Noguchi
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 5563092 (1996-10-01), Ohmi
patent: 5834327 (1998-11-01), Yamazaki et al.
patent: 6001727 (1999-12-01), Ohmi et al.
patent: 6100166 (2000-08-01), Sakaguchi et al.
patent: 6127199 (2000-10-01), Inoue et al.
patent: 6323070 (2001-11-01), Yamazaki
patent: 6357385 (2002-03-01), Ohmi et al.
patent: 6372608 (2002-04-01), Shimoda et al.
patent: 6376862 (2002-04-01), Yamazaki
patent: 6534382 (2003-03-01), Sakaguchi et al.
patent: 6624047 (2003-09-01), Sakaguchi et al.
patent: 6645830 (2003-11-01), Shimoda et al.
patent: 6646711 (2003-11-01), Sugano
patent: 6682963 (2004-01-01), Ishikawa
patent: RE38466 (2004-03-01), Inoue et al.
patent: 6700631 (2004-03-01), Inoue et al.
patent: 6818530 (2004-11-01), Shimoda et al.
patent: 6818852 (2004-11-01), Ohmi et al.
patent: 6830994 (2004-12-01), Mitsuki et al.
patent: 6849872 (2005-02-01), Yamazaki et al.
patent: 6885389 (2005-04-01), Inoue et al.
patent: 6975018 (2005-12-01), Ohmi et al.
patent: 7094655 (2006-08-01), Fukada et al.
patent: 7105423 (2006-09-01), Yamano et al.
patent: 7147740 (2006-12-01), Takayama et al.
patent: 7189624 (2007-03-01), Ito
patent: 7245331 (2007-07-01), Yamazaki et al.
patent: 7285476 (2007-10-01), Shimoda et al.
patent: 7332381 (2008-02-01), Maruyama et al.
patent: 7453090 (2008-11-01), Ito
patent: 2002/0020497 (2002-02-01), Ohmi et al.
patent: 2002/0030189 (2002-03-01), Ishikawa
patent: 2002/0067459 (2002-06-01), Sugano
patent: 2002/0113248 (2002-08-01), Yamagata et al.
patent: 2002/0153831 (2002-10-01), Sakakura et al.
patent: 2002/0155706 (2002-10-01), Mitsuki et al.
patent: 2003/0032210 (2003-02-01), Takayama et al.
patent: 2003/0062826 (2003-04-01), Seo et al.
patent: 2003/0203547 (2003-10-01), Sakaguchi et al.
patent: 2004/0050494 (2004-03-01), Ohmi et al.
patent: 2004/0129960 (2004-07-01), Maruyama et al.
patent: 2004/0164302 (2004-08-01), Arai et al.
patent: 2004/0217431 (2004-11-01), Shimada
patent: 2004/0238124 (2004-12-01), Nakamura
patent: 2005/0011455 (2005-01-01), Yamamoto et al.
patent: 2005/0023525 (2005-02-01), Ishikawa
patent: 2005/0052127 (2005-03-01), Sakata et al.
patent: 2005/0074963 (2005-04-01), Fujii et al.
patent: 2005/0136784 (2005-06-01), Seo et al.
patent: 2005/0158901 (2005-07-01), Yamazaki et al.
patent: 2005/0170565 (2005-08-01), Fujii et al.
patent: 2005/0282306 (2005-12-01), Yamanaka
patent: 2006/0266410 (2006-11-01), Ogita et al.
patent: 2006/0270236 (2006-11-01), Kusumoto et al.
patent: 2006/0273319 (2006-12-01), Dairiki et al.
patent: 2006/0275710 (2006-12-01), Yamazaki et al.
patent: 2009/0079572 (2009-03-01), Atsumi et al.
patent: 1574292 (2005-02-01), None
patent: 1 453 088 (2004-09-01), None
patent: 01-181570 (1989-07-01), None
patent: 02-154232 (1990-06-01), None
patent: 03-087299 (1991-04-01), None
patent: 04-170520 (1992-06-01), None
patent: 04-178633 (1992-06-01), None
patent: 04-299859 (1992-10-01), None
patent: 05-218365 (1993-08-01), None
patent: 06-291291 (1994-10-01), None
patent: 09-105896 (1997-04-01), None
patent: 11-020360 (1999-01-01), None
patent: 11-212116 (1999-08-01), None
patent: 2000-241822 (2000-09-01), None
patent: 2000-248243 (2000-09-01), None
patent: 2001-125138 (2001-05-01), None
patent: 2001-247827 (2001-09-01), None
patent: 2002-031818 (2002-01-01), None
patent: 2002-033464 (2002-01-01), None
patent: 2002-087844 (2002-03-01), None
patent: 2002-164354 (2002-06-01), None
patent: 2002-217391 (2002-08-01), None
patent: 2004-094492 (2004-03-01), None
patent: 2004-282050 (2004-10-01), None
patent: WO 2006/006611 (2006-01-01), None
patent: WO 2006/011664 (2006-02-01), None
Usami et al., “17.1 An SOI-Based 7.5 μm-Thick 0.15×0.15mm2RFID Chip,” ISSCC 2006 (Digest of Technical Papers, IEEE International Solid-State Circuits Conference), pp. 308-309 and 655.
Kouvatsos.D et al., “Single Crystal Silicon Thin Film Transistors Fabricated at Low Process Temperatures on Glass Substrates,” Electronics Letters, Apr. 11, 1996, vol. 32, No. 8, pp. 775-777.
Reiche.M et al., “Wafer Thinning: Techniques for Ultra-Thin Wafers,” Advanced Packaging (http://ap.pennnet.com/Articles/Article—Display.cfm?Section=Articles&Subsection=Display&ARTICLE—ID=169369), Mar. 1, 2003, Pennwell.
Office Action (Application No. 200610100198.6) Dated Jul. 31, 2009.
Reiche.M et al., “Wafer Thinning: Techniques for Ultra-Thin Wafers,” Advanced Packaging (http://ap.pennnet.com/Articles/Article—Display.cfm?Section=Articles&Subsection=Display&ARTICLE—ID=169369), Mar. 1, 2003, Pennwell, pp. 1-4.
Dairiki Koji
Kusumoto Naoto
Tsurume Takuya
Lee Hsien-ming
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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