Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-03-05
2010-06-29
Prenty, Mark (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE27086
Reexamination Certificate
active
07745867
ABSTRACT:
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.
REFERENCES:
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 4994893 (1991-02-01), Ozaki et al.
patent: 5045899 (1991-09-01), Arimoto
patent: 5357132 (1994-10-01), Turner
patent: 5475248 (1995-12-01), Takenaka
patent: 5629539 (1997-05-01), Aoki et al.
patent: 5665624 (1997-09-01), Hong
patent: 5962885 (1999-10-01), Fischer et al.
patent: 6060351 (2000-05-01), Parekh et al.
patent: 6093600 (2000-07-01), Chen et al.
patent: 6204115 (2001-03-01), Cho
patent: 6204186 (2001-03-01), Chaudhry et al.
patent: 6235603 (2001-05-01), Melnick et al.
patent: 6255159 (2001-07-01), Thakur
patent: 6329682 (2001-12-01), Parekh et al.
patent: 6359295 (2002-03-01), Lee et al.
patent: 6562679 (2003-05-01), Lee et al.
patent: 6563158 (2003-05-01), Houston et al.
patent: 6746915 (2004-06-01), Wu
patent: 2001/0030338 (2001-10-01), Noble
patent: 2002/0020883 (2002-02-01), Dennison
patent: 2002/0022317 (2002-02-01), Fukuzumi
patent: 2002/0064065 (2002-05-01), Sailing
patent: 2003/0094642 (2003-05-01), Houston et al.
Brady W. James
Keagy Rose Alyssa
Prenty Mark
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Integrated DRAM process/structure using contact pillars does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated DRAM process/structure using contact pillars, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated DRAM process/structure using contact pillars will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4241301