Nonvolatile memory array having modified channel region...

Details Nonvolatile memory array having modified channel region... Nonvolatile memory array having modified channel region...

2007-07-09

2010-06-29

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185280

Reexamination Certificate

active

07746694

ABSTRACT:
The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

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Yeh, Chih-Chieh et al., A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications, IEEE Transactions on Electron Devices, Vil. 52, No. 4, Apr. 2005, pp. 541-546.
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Sim, Sang-Pil, “Fully Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate-A Scaling Direction for 65nm and Beyond,” 2006 Symposium on VLSI technology Digest of Technical Papers, 2006 IEEE, 2 pp.

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