Semiconductor device

Details Semiconductor device Semiconductor device

2006-07-24

2010-10-05

Fahmy, Wael M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29266, C257SE25016, C257SE25026

Reexamination Certificate

active

07808049

ABSTRACT:
In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.

REFERENCES:
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patent: 6174822 (2001-01-01), Nagano et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2004/0178516 (2004-09-01), Ogata
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2006/0189075 (2006-08-01), Kanno
patent: 2003-273240 (2003-09-01), None
patent: 2004-087640 (2004-03-01), None
patent: 2004-273972 (2004-09-01), None
patent: 2006-237070 (2006-09-01), None
patent: WO 02/43151 (2002-05-01), None
Shimizu, “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, IEEE, 2001.
Japanese Notice of Reasons for Rejection w/ English translation thereof, issued in Japanese Patent Application No. 2005-272455 dated Apr. 6, 2010.

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