Method and arrangement for reducing power in bidirectional...

Details Method and arrangement for reducing power in bidirectional... Method and arrangement for reducing power in bidirectional...

2009-01-22

2010-12-28

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

C326S038000, C326S056000, C326S082000

Reexamination Certificate

active

07859294

ABSTRACT:
An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z signal to an output driver, and feeding back the output signal to an input driver when driving the output signal. The method can float the I/O port when the Hi-Z signal is asserted on the output driver or drive the I/O port as an input when the Hi-Z signal is asserted on the output driver. The method can refrain from floating a signal back into the I/O port when driving a signal out by driving a constant logical zero back into the I/O port or driving a constant logical one back or by maintaining a last value driven.

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Advanced Micro Devices, Inc.,Programmable Array Logic, copyright 1984, p. 1-20 (3 pages total), available from Advanced Micro Devices, Inc., Sunnyvale, California, USA.
Xilinx, Inc.,The Programmable Gate Array Design Handbook, copyright 1986, pp. 2-23 (3 pages total), available from Xilinx, Inc., San Jose, California, USA.

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