Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2008-02-26
2010-02-09
Thai, Tuan V (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S005000, C711S130000, C711S151000, C365S200000, C345S558000
Reexamination Certificate
active
07660951
ABSTRACT:
Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.
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Jenkins Steven K.
Weaver Laura A.
Choe Yong
Daugherty Patrick J.
Driggs, Hogg, Daugherty & Del Zoppo Co., LPA
Inernational Business Machines Corporation
Thai Tuan V
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