Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-12-12
2010-06-08
Chace, Christian P (Department: 2187)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S055000, C714S027000, C714S048000, C711S133000, C711S148000, C370S217000, C709S239000
Reexamination Certificate
active
07734957
ABSTRACT:
The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.
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Japan Patent Office (JPO) office action for JPO patent application JP2006-264147 (Jan. 8, 2009).
Japan Patent Office (JPO) office action for JPO patent application JP2006-264147 (May 26, 2009).
Fujibayashi Akira
Hosoya Mutsumi
Nakamura Shuji
Chace Christian P
Hitachi , Ltd.
Otto Alan
Townsend and Townsend / and Crew LLP
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