Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-10-06
2010-02-09
Fahmy, Wael (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE29256, C257S347000, C438S163000
Reexamination Certificate
active
07659579
ABSTRACT:
A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
REFERENCES:
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5587604 (1996-12-01), Machesney et al.
patent: 5693959 (1997-12-01), Inoue et al.
patent: 5767549 (1998-06-01), Chen et al.
patent: 6048756 (2000-04-01), Lee et al.
patent: 6306691 (2001-10-01), Koh
patent: 6437404 (2002-08-01), Xiang et al.
patent: 6512269 (2003-01-01), Bryant et al.
patent: 6624475 (2003-09-01), Bryant et al.
patent: 6960806 (2005-11-01), Bryant et al.
patent: 7009265 (2006-03-01), Anderson et al.
patent: 2002/0175374 (2002-11-01), Iwata et al.
patent: 2004/0219724 (2004-11-01), Park et al.
patent: 2005/0045949 (2005-03-01), Lin et al.
patent: 2005/0110079 (2005-03-01), Nowak
patent: 2005/0118826 (2005-06-01), Boyd et al.
patent: 2005/0164433 (2005-07-01), Doris et al.
patent: 2005/0189589 (2005-09-01), Zhu et al.
patent: 2006/0001095 (2006-01-01), Doris et al.
Plummer, “Silicon VLSI Fundamentals, Practice and Modeling”, 2000, Prentice Hall, p. 71.
Anderson et al., U.S. Appl. No. 11/869,766, BUR920060049US2, Office Action Communication, Jul. 14, 2009, 14 Pages.
Anderson Brent A.
Bryant Andres
Nowak Edward J.
Williams Richard Q.
Canale Anthony
Fahmy Wael
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Wright Tucker
LandOfFree
FETS with self-aligned bodies and backgate holes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with FETS with self-aligned bodies and backgate holes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FETS with self-aligned bodies and backgate holes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4230741