Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2007-05-14

2010-11-16

Nguyen, Ha Tran T (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S278000

Reexamination Certificate

active

07834402

ABSTRACT:
To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1are connected to power supply. Gate of the P-channel transistor P1is connected to input terminal IN. Gate of N1is connected to IN. Drain of N1is connected to OUT. Cathode of diode D1is connected to power supply, anode of D1being connected to OUT. Cathode of diode D2is connected to OUT, anode of D2being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer of D1includes a projection plane of a region of an n+ diffusion layer of N, and a projection plane of a region of an n+ diffusion layer of the diode D2includes a projection plane of a region of a p+ diffusion layer of P1.

REFERENCES:
patent: 2005/0264334 (2005-12-01), Yoneda
patent: 2005-341354 (2005-12-01), None
Andrews et al., “Single Event Error Immune CMOS RAM”, IEEE Trans. on Nucl. Sci., vol. NS-29, No. 6, pp. 2040-2043 (Dec. 1982).
Nikkei Electronics, pp. 82-99 (Oct. 2005).

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