Semiconductor integrated circuit designing method,...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07844923

ABSTRACT:
A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having a high-potential power supply end connected to VDDand a low potential power supply end connected to a pseudo-power supply line VSSV, and a logic gate cell L and a layout cell L each having a high-potential power supply end connected to a pseudo-power supply line VDDVand a low potential power supply end connected to VSS, are prepared. Logic simulation is performed on the assumption of a state immediately before power cut-off using a net list. The logic gate cell H is used as a primitive logic gate having an output state of “H” and the logic gate cell L is used as a primitive logic gate having an output state of “L”, thereby changing the net list. A layout is generated using the layout cells H and L.

REFERENCES:
patent: 6477654 (2002-11-01), Dean et al.
patent: 7458052 (2008-11-01), Chandra et al.
patent: 2003/0208725 (2003-11-01), Shibata et al.
patent: 2005/0091629 (2005-04-01), Eisenstadt et al.
patent: 2003-218210 (2003-07-01), None
patent: 2005-039334 (2005-02-01), None
Min, Kyeong-Sik et al., “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era,” ISSCC, Session 22, Paper 22.8, University of Tokyo, 2003, IEEE Tokyo, Japan.

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