Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-19
2010-11-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07844923
ABSTRACT:
A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having a high-potential power supply end connected to VDDand a low potential power supply end connected to a pseudo-power supply line VSSV, and a logic gate cell L and a layout cell L each having a high-potential power supply end connected to a pseudo-power supply line VDDVand a low potential power supply end connected to VSS, are prepared. Logic simulation is performed on the assumption of a state immediately before power cut-off using a net list. The logic gate cell H is used as a primitive logic gate having an output state of “H” and the logic gate cell L is used as a primitive logic gate having an output state of “L”, thereby changing the net list. A layout is generated using the layout cells H and L.
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Min, Kyeong-Sik et al., “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era,” ISSCC, Session 22, Paper 22.8, University of Tokyo, 2003, IEEE Tokyo, Japan.
Ito Minoru
Yoshimoto Yutaka
Chiang Jack
McDermott Will & Emery LLP
Panasonic Corporation
Tat Binh C
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