Method and device for classifying cells in a layout into a...

Details Method and device for classifying cells in a layout into a... Method and device for classifying cells in a layout into a...

2007-08-01

2010-02-16

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S030000

Reexamination Certificate

active

07665051

ABSTRACT:
A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.

REFERENCES:
patent: 5249134 (1993-09-01), Oka
patent: 6308143 (2001-10-01), Segawa
patent: 7024640 (2006-04-01), Buchanan
patent: 2003/0154461 (2003-08-01), Pierrat
patent: 2003/0159120 (2003-08-01), Baader et al.

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