Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-11-06
2010-10-05
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C365S185090
Reexamination Certificate
active
07810016
ABSTRACT:
A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the ECC circuit when a data width of the write data is less than a predetermined data width.
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Japanese Patent Office issued a Japanese Office Action dated Sep. 28, 2009, Application No. 2005327011.
Abraham Esaw T
NEC Electronics Corporation
Young & Thompson
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