Semiconductor device, display panel and electronic equipment

Electronic digital logic circuitry – Interface – Logic level shifting

Reexamination Certificate

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Details

C326S088000, C327S390000, C345S092000

Reexamination Certificate

active

07843221

ABSTRACT:
The present invention provides a semiconductor device having a buffer circuit formed on an insulating substrate using single-channel type thin film transistors, wherein the buffer circuit has an output stage which including first and second thin film transistors connected in series between first and second power sources, and the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor.

REFERENCES:
patent: 5870071 (1999-02-01), Kawahata
patent: 2005-149624 (2005-06-01), None

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