Coherent access register data transfer device and methods...

Details Coherent access register data transfer device and methods... Coherent access register data transfer device and methods...

2006-08-25

2010-06-22

Kindred, Alford W (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S035000, C710S055000, C710S065000, C710S305000, C711S141000

Reexamination Certificate

active

07743184

ABSTRACT:
Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

REFERENCES:
patent: 4805098 (1989-02-01), Mills et al.
patent: 5892978 (1999-04-01), Munguia et al.

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