Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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Reexamination Certificate

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07830738

ABSTRACT:
A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line.

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John Barth et al., “A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier”, IEEE International Solid-Stat Circuits Conference, ISSCC 2007/Session 27/DRAM and eRAM/27.1, Feb. 14, 2007, Digest of Technical Papers, pp. 486-487, 617, 27.1.1-27.1.7.
Advance Program, ISSCC 2007 IEEE International Solid-State Circuits Conference, Feb. 11-15, 2007, Conference Theme: The 4 Dimensions of IC Innovation, San Francisco Marriott Hotel, pp. 2-3, 80-81.

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