Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S452000, C257S484000

Reexamination Certificate

active

07851873

ABSTRACT:
The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.

REFERENCES:
patent: 6118152 (2000-09-01), Yamaguchi et al.
patent: 6642599 (2003-11-01), Watabe et al.
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patent: 9-45762 (1997-02-01), None
patent: 9-97832 (1997-04-01), None
patent: 11-312805 (1999-11-01), None
patent: 10-2005-0063315 (2005-06-01), None
Kazuo Imai, “ A New Dielectric Isolation Method Using Porous Silicon”, Solid-State Electronics, vol. 24, 1981, pp. 159-161, 163 and 164.

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