Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-04
2010-10-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07814456
ABSTRACT:
The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post-planarization topography of the wafer layer.
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Gupta Puneet
Kahng Andrew B.
Martine & Penilla & Gencarella LLP
Siek Vuthe
Tela Innovations, Inc.
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