Memory cell arrangements

Details Memory cell arrangements Memory cell arrangements

2006-09-22

2010-11-23

Fahmy, Wael M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C438S626000, C438S631000, C438S633000

Reexamination Certificate

active

07838921

ABSTRACT:
A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

REFERENCES:
patent: 5120670 (1992-06-01), Bergmont
patent: 5372969 (1994-12-01), Moslehi
patent: 2004/0161881 (2004-08-01), Shin et al.
patent: 2006/0240612 (2006-10-01), Lee

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