OTP memory cell, OTP memory, and method of manufacturing OTP...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S379000, C257SE21666, C257SE27085, C257SE27102

Reexamination Certificate

active

07808054

ABSTRACT:
An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an upper electrode being in contact with the first trench-type insulating region and formed on the lower electrode with the first insulating film interposed therebetween; and a gate electrode being in contact with the second trench-type insulating region and formed on a channel region with the second insulating film interposed therebetween, in which a shape of at least a part of an end of the lower electrode forming region in contact with the first insulating film is sharper than a shape of an end of the channel region in contact with the second insulating film.

REFERENCES:
patent: 4502208 (1985-03-01), McPherson
patent: 5146307 (1992-09-01), Kaya
patent: 6421293 (2002-07-01), Candelier et al.
patent: 2004/0047218 (2004-03-01), Peng
patent: 2006/0192245 (2006-08-01), Oosawa
patent: 2005-504434 (2005-02-01), None

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