Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-06-30
2010-06-29
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S012000, C714S048000, C714S798000
Reexamination Certificate
active
07747932
ABSTRACT:
Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
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Biswas Arijit
Emer Joel S.
Mukherjee Shubhendu S.
Raasch Steven E.
Racunas Paul B.
Abraham Esaw T
Intel Corporation
Lane Thomas R.
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