SOI CMOS compatible multiplanar capacitor

Details SOI CMOS compatible multiplanar capacitor SOI CMOS compatible multiplanar capacitor

2007-09-19

2010-06-01

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27092, C438S243000

Reexamination Certificate

active

07728371

ABSTRACT:
An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

REFERENCES:
patent: 5759907 (1998-06-01), Assaderaghi et al.
patent: 5770875 (1998-06-01), Assaderaghi et al.
patent: 6057188 (2000-05-01), El-Kareh et al.
patent: 6867450 (2005-03-01), Kito et al.

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