Read-data stage circuitry for DDR-SDRAM memory controller

Details Read-data stage circuitry for DDR-SDRAM memory controller Read-data stage circuitry for DDR-SDRAM memory controller

2006-10-13

2010-06-15

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S500000, C711S105000, C711S167000, C365S189011, C365S193000

Reexamination Certificate

active

07739539

ABSTRACT:
A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.

REFERENCES:
patent: 6782459 (2004-08-01), Ware
patent: 7313715 (2007-12-01), Yoo et al.
patent: 2005/0138277 (2005-06-01), Koo
patent: 2006/0230250 (2006-10-01), Klint et al.
patent: WO-2008/048835 (2008-04-01), None
“International Application No. PCT/US07/80934, International Search Report mailed Mar. 7, 2008”, 2 pgs.
“International Application No. PCT/US07/80934, Written Opinion mailed Mar. 7, 2008”, 3 pgs.

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