Interlevel dielectric fabrication process

Details Interlevel dielectric fabrication process Interlevel dielectric fabrication process

1985-10-31

1989-01-24

Lacey, David L.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156663, B44C 122, B23P 1500, C03C 1500

Patent

active

047999926

ABSTRACT:
A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.

REFERENCES:
patent: 4356040 (1982-10-01), Fu et al.
patent: 4451326 (1984-05-01), Gwozdz
patent: 4476621 (1984-10-01), Bopp et al.
patent: 4518629 (1985-05-01), Jeuch
patent: 4590663 (1986-05-01), Haken
patent: 4659427 (1987-04-01), Barry et al.
Adams et al., "Planarization of Phosphorus-Doped Silicon Dioxide", J. Electrochem. Soc, 2/81, pp. 423-429.

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