Addressing strategy for Viterbi metric computation

Details Addressing strategy for Viterbi metric computation Addressing strategy for Viterbi metric computation

2005-06-20

2010-10-19

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000, C714S794000, C714S796000, C375S272000, C375S341000

Reexamination Certificate

active

07818654

ABSTRACT:
There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

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