Method and semiconductor structure for monitoring etch...

Details Method and semiconductor structure for monitoring etch... Method and semiconductor structure for monitoring etch...

2007-10-19

2010-11-09

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C438S014000, C438S018000

Reexamination Certificate

active

07829889

ABSTRACT:
By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

REFERENCES:
patent: 7176485 (2007-02-01), Leidy
patent: 7705352 (2010-04-01), Feustel et al.
patent: EP 0 273 251 (1987-12-01), None
patent: 2001102405 (2001-04-01), None
Transmittal letter from foreign associate dated Jan. 15, 2008.
Translation of Official Communication Issued: Nov. 9, 2007.

Affiliated with

Also associated with

Rating

Method and semiconductor structure for monitoring etch... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and semiconductor structure for monitoring etch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and semiconductor structure for monitoring etch... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4179440