Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-19
2010-12-21
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07856608
ABSTRACT:
A model generation method for generating a semiconductor device model used for power supply noise analysis, is performed by, calculating noise values for various circuit elements based on current source noise waveforms calculated in accordance with a current flowing from a power supply when a state of the elements changes, determining the time when the change of state of the elements causing the current source noise occurs in relation to successive timing windows each having a predetermined time width, and calculating noise by unit time and adding up for each divided unit time the noise value calculated for all elements whose timing window is present in the unit time, wherein a timing determination unit determines the worst case and other noise generation timing based on the noise generated in each unit time.
REFERENCES:
patent: 7246335 (2007-07-01), Murgai et al.
patent: 2005/0268264 (2005-12-01), Nagai
patent: 2008/0052654 (2008-02-01), Rahmat et al.
patent: A 2004-234618 (2004-08-01), None
patent: A 2005-339060 (2005-12-01), None
Fujitsu Limited
Greer Burns & Crain Ltd
Levin Naum B
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