Structure and method for detecting errors in a multilevel...

Details Structure and method for detecting errors in a multilevel... Structure and method for detecting errors in a multilevel...

2008-10-14

2010-06-01

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07730383

ABSTRACT:
An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

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