Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-02-21

2010-02-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S207000

Reexamination Certificate

active

07663941

ABSTRACT:
This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit lines, and transmitting the data of the memory cells; transfer gates connected between the bit lines and the sense nodes; a latch circuit latching a first high level potential to one of the pair of sense nodes, and latching a low level potential to the other sense node of the pair of sense nodes; and a level shifter applying a second high level potential higher than the first high level potential to one of the pair of bit lines according to the potentials latched to the pair of sense nodes during a data write operation or a data write-back operation.

REFERENCES:
patent: 6567330 (2003-05-01), Fujita et al.
patent: 7277341 (2007-10-01), Fujita et al.
patent: 7301838 (2007-11-01), Waller et al.
patent: 7539043 (2009-05-01), Ohsawa
patent: 2007/0279979 (2007-12-01), Fujita
patent: 2008/0198673 (2008-08-01), Fujita
patent: 2005-302234 (2005-10-01), None
Takashi Ohsawa, et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, 2005 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. 48, 2005, 5 pages.

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