Semiconductor device and method for fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S501000, C257S506000, C257S510000, C257SE21279, C257SE21696, C438S124000, C438S112000

Reexamination Certificate

active

07829924

ABSTRACT:
A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.

REFERENCES:
patent: 2005/0032275 (2005-02-01), Toda et al.
patent: 5-21591 (1993-01-01), None
Yang et al., “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEDM 2004 Late News, 2004.

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