Vertical and trench type insulated gate MOS semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S565000, C257S370000, C257SE21384, C257SE29040, C438S270000

Reexamination Certificate

active

07737490

ABSTRACT:
A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

REFERENCES:
patent: 5801408 (1998-09-01), Takahashi
patent: 6221721 (2001-04-01), Takahashi
patent: 6380586 (2002-04-01), Yoshikawa
patent: 2003/0116807 (2003-06-01), Matsuda
patent: 2004/0188803 (2004-09-01), Matsuda
patent: 2006/0163649 (2006-07-01), Otsuki
patent: 10-163483 (1998-06-01), None
patent: 2000-228519 (2000-08-01), None
patent: 2001-274400 (2001-10-01), None
patent: 2003-258253 (2003-09-01), None
patent: 2006-210547 (2006-08-01), None

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