Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-31
2010-12-28
Alphonse, Fritz (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S746000, C714S758000
Reexamination Certificate
active
07861140
ABSTRACT:
A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.
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Alphonse Fritz
GLOBALFOUNDRIES Inc.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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