Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2008-03-25

2010-11-09

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S205000, C257SE21631, C257SE21061, C438S217000, C438S276000, C438S289000, C438S291000

Reexamination Certificate

active

07829957

ABSTRACT:
A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.

REFERENCES:
patent: 4849368 (1989-07-01), Yamashita et al.
patent: 5514605 (1996-05-01), Asai et al.
patent: 6703638 (2004-03-01), Danzilio
patent: 7183592 (2007-02-01), Hwang
patent: 2005/0263789 (2005-12-01), Hwang
patent: 2006/0284212 (2006-12-01), Murayama et al.
patent: 2007/0295991 (2007-12-01), Kato et al.
patent: 8-116034 (1996-05-01), None
patent: 3483716 (2003-10-01), None
English language Abstract of JP 8-116034.
English language Abstract of JP 10-173137.

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