Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-29
2010-06-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07735047
ABSTRACT:
Disclosed are processor-implemented methods for technology mapping a logic network onto programmable logic resources of a programmable logic device. The methods include determining respective Boolean flexibility values for a plurality of functionally equivalent mappings of the logic network onto the programmable logic resources, selecting one of the mappings as a function of the respective Boolean flexibility values, and storing the selected mapping.
REFERENCES:
patent: 7100141 (2006-08-01), Ratchev et al.
patent: 7131098 (2006-10-01), Darringer et al.
patent: 7194723 (2007-03-01), Hwang et al.
patent: 7249329 (2007-07-01), Baeckler et al.
Cong et al; On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping; IEEE Transactions on computer-aided design, vol. 2. No. 2, Jun. 1994, pp. 137-148.
Andrew Ling et al.; “FPGA Technology Mapping: A Study of Optimality”; DAC 2005; Jun. 13-17, 2005; Copyright 2005 ACM; pp. 1-6.
Ellen M. Sentovich et al.; “Multiple Boolean Relations”; International Workshop on Logic Synthesis; May 1, 1993; pp. 1-13.
Jason Cong et al.; “Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution”; In International Symposium on Field-Programmable Gate Arrays; 1999; pp. 29-35.
Alan Mischenko et al.; “SAT=Based Complete Don't-Care Computation for Network Optimization” Proceedings of the Design, Automation and Test in Europe Conference and Exhibition; 2005; IEEE; pp. 412-417.
Shigeru Yamashita et al.; “SPFD: A New Method to Express Functional Flexibility”; IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems; vol. 19, No. 8; Aug. 8, 2000; copyright 2000 IEEE; pp. 840-849.
Robert J. Francis et al.; “Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays”; 27th ACM/IEEE Design Automation Conference; Copyright 1990 IEEE; pp. 613-619.
Jason H. Anderson et al.; “Power-Aware Technology Mapping for LUT-Based FPGAs”; IEEE International Conference on Field-Programmable Technology; 2002; Copyright 2002 IEEE; pp. 211-218.
Jason Cong et al.; “FlowMap: An Optimal Technology Mapping, Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs”; lEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; Jan. 1994; Copyright 1994 IEEE; pp. 1-12.
Jason Cong et al.; “On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping”; IEEE Transaction on VLSI Systems; vol. 2, No. 2; Jun. 1994; Copyright 1994 IEEE; pp. 137-148.
B. Kumthekar et al.; “Power Optimisation of FPGA-Based Designs Without Rewiring”; IEE Proc.-Comput. Digit. Tech.; vol. 147, No. 3; May 2000; pp. 167-174.
Anderson Jason H.
Wang Qiang
Cartier Lois D.
Chiang Jack
Maunu LeRoy D.
Tat Binh C
Xilinx , Inc.
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