Packaging substrate and method for fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S786000, C438S108000

Reexamination Certificate

active

07812460

ABSTRACT:
A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications.

REFERENCES:
patent: 6445075 (2002-09-01), Scanlan et al.
patent: 6779783 (2004-08-01), Kung et al.
patent: 6809262 (2004-10-01), Hsu
patent: 2007/0222072 (2007-09-01), Chang et al.
patent: 2009/0308652 (2009-12-01), Shih
patent: 2010/0007015 (2010-01-01), Gallegos

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