Semiconductor device, wafer and method of designing and...

Details Semiconductor device, wafer and method of designing and... Semiconductor device, wafer and method of designing and...

2007-12-06

2010-11-23

Tran, Minh-Loan T (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S128000, C438S622000, C257SE21575, C257SE21582, C257SE21590

Reexamination Certificate

active

07838408

ABSTRACT:
A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration.

REFERENCES:
patent: 6888254 (2005-05-01), Yamaguchi et al.
patent: 2003/0104690 (2003-06-01), Matsubara
patent: 2003/0148558 (2003-08-01), Kubo et al.
patent: 2005/0064091 (2005-03-01), Yamazaki
Tatsuhiko Higashiki, “Photolithography: Practical Fundamentals and Challenges”, ED Research Co., Ltd., Jul. 1, 2002.
Tatsuhiko Higashiki, “Photolithography II: Measurement and Control”, ED Research Co., Ltd., Jun. 10, 2003.

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