Semiconductor device and method for manufacturing same

Details Semiconductor device and method for manufacturing same Semiconductor device and method for manufacturing same

2008-10-06

2010-10-26

Ha, Nathan W (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07821074

ABSTRACT:
The present invention provides a semiconductor device includes: an element isolation region configured to be formed in a semiconductor substrate; a P-type field effect transistor configured to be formed in a first element formation region of the semiconductor substrate for which isolation by the element isolation region is carried out; an N-type substrate region configured to be formed in the semiconductor substrate for which isolation by the element isolation region is carried out, arsenic being ion-implanted into the N-type substrate region; a nickel silicide layer configured to be formed on the N-type substrate region; a first insulating film configured to cover the P-type field effect transistor and have compressive stress; and a second insulating film configured to cover the N-type substrate region and have tensile stress or compressive stress lower than the compressive stress of the first insulating film.

REFERENCES:
patent: 7238578 (2007-07-01), Burbach et al.
patent: 2007/0200179 (2007-08-01), Chen
patent: 2008/0179638 (2008-07-01), Dyer et al.
patent: 2008/0303068 (2008-12-01), Grill et al.
Yang et al., “Dual Streee Liner for High Performance sub-45nm Gate Lenght SOI CMOS Manufacturing”, IEDM Tech. Dig., pp. 1075, 2004.
Yun et al. “Abnormal Oxidation of Formed on Arsenic Doped Substrate”, Electrochemical and Solid-State Letters, 7 (4) G83-G85, (2004).

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