Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-09-12
2010-11-09
Graybill, David E (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S682000
Reexamination Certificate
active
07829461
ABSTRACT:
A semiconductor device fabrication method by which the thermal stability of nickel silicide can be improved. Nickel (or a nickel alloy) is formed over a semiconductor substrate on which a gate region, a source region, and a drain region are formed. Dinickel silicide is formed by performing a first annealing step, followed by a selective etching step. By performing a plasma treatment step, plasma which contains hydrogen ions is generated and the hydrogen ions are implanted in the dinickel silicide or the gate region, the source region, and the drain region under the dinickel silicide. The dinickel silicide is phase-transformed into nickel silicide by performing a second annealing step.
REFERENCES:
patent: 7279422 (2007-10-01), Choi
patent: 2002/0146904 (2002-10-01), Buynoski et al.
patent: 2005/0202664 (2005-09-01), Jawarani
patent: 2006/0267117 (2006-11-01), Jaiswal
patent: 2007/0166974 (2007-07-01), Uchino et al.
patent: 2007/0166975 (2007-07-01), Uchino et al.
patent: 2007/0167009 (2007-07-01), Chen et al.
patent: 2007/0173047 (2007-07-01), Lu et al.
patent: 2007/0202695 (2007-08-01), Kawamura et al.
patent: 2007/0254477 (2007-11-01), Muraoka et al.
patent: 2007/0254479 (2007-11-01), Fang et al.
patent: 2007/0257303 (2007-11-01), Liu et al.
patent: 2008/0242035 (2008-10-01), Futase et al.
patent: 2009/0008727 (2009-01-01), Yamauchi et al.
patent: 2009/0011566 (2009-01-01), Okada et al.
patent: 2009/0212021 (2009-08-01), Bernhard et al.
patent: 58-213465 (1983-12-01), None
patent: 2004-128501 (2004-04-01), None
Derwent Abstracted-Pub-No. KR 2006007108. Kang. 1 drawing. Jan. 2006.
“Nickel-silicidation process using hydrogen implantation.” Choi. Electronics Letters. Mar. 2004 vol. 40 No. 6.
M. Tinani et al.; “In situ real-time studies of nickel silicide phase formation”; J. Vac. Sci. Technol. B19(2), Mar./Apr. 2001, pp. 376-383.
D. Mangelinck et al.; “Effect of Co2Pt, and Au additions on the stability and epitaxy of NiSi2films on (111)Si”, Journal of Applied Physics; vol. 84, No. 5; Sep. 1, 1998; pp. 2583-2590.
Wei Huang et al.; “Effect of a thin W interlayer on the thermal stability and electrical characteristics of NiSi film”, J. Vac. Sci. Technol. B23(6), Nov./Dec. 2005, pp. 2304-2308.
Chao-Chun Wang et al.; “Formation of NiSi-Silicided p+n. Shallow Junctions Using Implant -Through-Silicide and Low Temperature Furnace Annealing”, Journal of the Electrochemical Society, vol. 150, No. 9; Jul. 24, 2003; pp. G557-G562.
Chel-Jong Choi et al, ; “Effects of Hydrogen Implantation on the Structural and Electrical Properties of Nickel Silicide”, Journal of the Electrochemical Society, vol. 149, No. 9; Jul. 16, 2002, pp. G517-G521.
D. Z. Chi et al.: “Addressing Materials and Process-Integration Issues of NiSi Silicide Process Using Impurity Engineering”, Institute of Materials Research and Engineering; 2004 IEEE, Mar. 15, 2004, pp. 113-118.HI.
Jang-Gn Yun et al.: “Abnormal Oxidation of Nickel Silicideon N-Type Substrate and Effect of Preamorphization Implantation”, Japanese Journal of Applied Physics; vol. 43, No. 10, Oct. 8, 2004, pp. 6998-6999.
Jorge A. Kittl et al.; “Applications of Ni-based silicides to 45nm CMOS and Beyond”. Mat. Res. Soc. Symp. Proc. vol. 810; Apr. 12, 2004; pp. C2.1.1-C2.1.12.
Kwan-Woo Do et al; “Formation of Low-Resistivity Nickel Silicide with High Temperature Stability from Atomic-Layer-Deposited Nickel Thin Film”, Japanese Journal of Applied Physics; vol. 45 No. 4B, Apr. 25, 2006; pp. 2975-2979.
Akiyama Shin-ichi
Kawamura Kazuo
Fujitsu Semiconductor Limited
Graybill David E
Westerman Hattori Daniels & Adrian LLP
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