Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2008-06-30
2010-11-16
Yoha, Connie C (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S193000, C365S230060, C365S189050
Reexamination Certificate
active
07835204
ABSTRACT:
A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.
REFERENCES:
patent: 5493241 (1996-02-01), Landry et al.
patent: 6982923 (2006-01-01), Ootsuki
patent: 7248512 (2007-07-01), Shin
patent: 7397727 (2008-07-01), Schnell et al.
patent: 7417917 (2008-08-01), Lee et al.
patent: 1020070002841 (2007-01-01), None
patent: 1020070073027 (2007-07-01), None
Kim Kyung-Whan
Park Eun-Young
Hynix / Semiconductor Inc.
IP & T Group LLP
Yoha Connie C
LandOfFree
Semiconductor memory device for generating column address does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device for generating column address, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for generating column address will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4159446