Systems and methods for lowering interconnect capacitance...

Details Systems and methods for lowering interconnect capacitance... Systems and methods for lowering interconnect capacitance...

2008-07-04

2010-10-26

Wojciechowicz, Edward (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

C257S532000, C257S545000, C257S664000, C257S698000, C257S774000, C257S777000

Reexamination Certificate

active

07821108

ABSTRACT:
Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential. Regardless of the particular embodiment used, raising the midpoint-voltage level of the signals on the TWIs relative to the substrate decreases capacitance, which increases the frequency of the data which can propagate through the TWIs while potentially reducing the signaling power.

REFERENCES:
patent: 6589180 (2003-07-01), Erikson et al.
U.S. Appl. No. 12/106,552, filed Apr. 21, 2008, Hollis.
U.S. Appl. No. 12/101,770, filed Apr. 11, 2008, Lee.

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