MOS device with substrate potential elevation

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S355000, C257S546000

Reexamination Certificate

active

07838924

ABSTRACT:
An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor200is formed in or on the p-layer (38) comprising a n+ source (43), n+drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region. The terminal of the functional circuit (24, PAD) is coupled to the cathode (36) of the Nwell diode, and the anode (37) of the Nwell diode is connected in series with a path from the drain (44) to the source (43) of the NMOS transistor (200).

REFERENCES:
patent: 6624487 (2003-09-01), Kunz et al.
patent: 6696708 (2004-02-01), Hou et al.
patent: 6713841 (2004-03-01), Gossner
patent: 7282767 (2007-10-01), Duvvury et al.
patent: 2008/0067615 (2008-03-01), Kim

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