Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2008-08-22
2010-10-19
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S137000, C711S204000, C711S213000
Reexamination Certificate
active
07818514
ABSTRACT:
A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
REFERENCES:
patent: 5860126 (1999-01-01), Mittal
patent: 5887151 (1999-03-01), Raz et al.
patent: 6247025 (2001-06-01), Bacon
patent: 6513100 (2003-01-01), Clift
patent: 6782440 (2004-08-01), Miller
Roth, et al., “Effective Jump-Pointer Prefetching for Linked Data Structures”, Computer Architecture News, ACM, New York, NY, US, vol. 27, No. 2, May 1999, pp. 111-121, XP000975502 ISSN: 0163-5964.
Luk, et al., “Compiler-Based Prefetching for Recursive Data Structures”, ACM Sigplan Notices, ACM, Association for Computing Machinery, New York, NY, US, vol. 31, No. 9, Sep. 1996, ISSN: 0362-1340.
Karlsson, et al., “A prefetching technique for irregular accesses to linked data structures”, High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on Touluse, France Jan. 8-12, 2000, Los Alamitos, CA, USA, IEEE Comput. Soc. US, Jan. 8, 2000, pp. 206-217, XP010371910 ISBN: 0-7695-0550-3.
Japanese Published Unexamined Patent Publication No. 2002-215456 dated Aug. 2, 2002.
Luk, et al., “Compiler-Based Prefetching for Recursive Data Structures”, ACM Sigplan Notices, ACM, Association for Computing Machinery, New York, NY, US, vol. 31, No. 9, Sep. 1996, ISSN: 0362-1340; and.
Karlsson, et al., “A prefetching technique for irregular accesses to linked data structures”, High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on Touluse, France Jan. 8-12.
Blumrich Matthias A.
Chen Dong
Coteus Paul W.
Gara Alan G.
Giampapa Mark E.
International Business Machines - Corporation
Morris, Esq. Daniel P.
Nguyen Than
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Low latency memory access and synchronization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low latency memory access and synchronization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low latency memory access and synchronization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4156635