Method for designing a semiconductor integrated circuit...

Details Method for designing a semiconductor integrated circuit... Method for designing a semiconductor integrated circuit...

Filed on

2006-07-14

Date issued

2010-11-30

Examiner

Doan, Nghia M (Department: 2825)

Patent Class

Computer-aided design and analysis of circuits and semiconductor

SubClass

Nanotechnology related integrated circuit design

Other Related Categories

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S030000

Type

Reexamination Certificate

Status

active

Patent number

07844934

Description

ABSTRACT:
According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.

REFERENCES:
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patent: 6680539 (2004-01-01), Nohsoh et al.
patent: 7208350 (2007-04-01), Kawashima et al.
patent: 2002/0100005 (2002-07-01), Anderson et al.
patent: 2003/0229479 (2003-12-01), Smith et al.
patent: 2004/0098674 (2004-05-01), Vuong et al.
patent: 2004/0230769 (2004-11-01), Kawashima et al.
patent: 2001-156072 (2001-06-01), None
patent: 2004-288685 (2004-10-01), None

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