Semiconductor memory device and operation method of the same

Details Semiconductor memory device and operation method of the same Semiconductor memory device and operation method of the same

2007-12-27

2010-11-23

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S230060, C365S233100

Reexamination Certificate

active

07839705

ABSTRACT:
A semiconductor memory device has a timing margin for internal operations. The semiconductor memory device can activate an internal control signal for controlling an external address sooner than an internal control signal for controlling an external command to secure a sufficient time for data access. The semiconductor memory device includes a command decoding circuit configured to decode an external command to output an internal command signal for an internal operation corresponding to the external command, a control circuit configured to generate a strobe signal for controlling the internal operation in response to the internal command signal and an internal address signal by decoding an address signal received from outside such that the internal address signal activates sooner than the strobe signal, and a column decoding circuit configured to generate a data access signal when both the internal address signal and the strobe signal are activated.

REFERENCES:
patent: 6295245 (2001-09-01), Tomita et al.
patent: 6317369 (2001-11-01), Kubo et al.
patent: 6671787 (2003-12-01), Kanda et al.
patent: 7414899 (2008-08-01), Oh et al.
patent: 2000-222879 (2000-08-01), None

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